title: Scheduling problem to minimize the maximum lateness for parallel processors
metadata.name: dc.contributor.author
metadata.value: Grigoreva, Natalia S.
metadata.lang: -
metadata.name: dc.date.accessioned
metadata.value: 2017-02-09T09:19:42Z
metadata.lang: -
metadata.name: dc.date.available
metadata.value: 2017-02-09T09:19:42Z
metadata.lang: -
metadata.name: dc.date.issued
metadata.value: 2016-12
metadata.lang: -
metadata.name: dc.identifier.citation
metadata.value: Grigoreva N. S. Scheduling problem to minimize the maximum lateness for parallel processors. Vestnik of Saint Petersburg University. Series 10. Applied mathematics. Computer science. Control processes, 2016, issue 4, pp. 51–65.
metadata.lang: en_GB
metadata.name: dc.identifier.other
metadata.value: 10.21638/11701/spbu10.2016.405
metadata.lang: -
metadata.name: dc.identifier.uri
metadata.value: http://hdl.handle.net/11701/5996
metadata.lang: -
metadata.name: dc.description.abstract
metadata.value: The problem of minimizing the maximum lateness while scheduling tasks to parallel identical
  processors is a classical combinatorial optimization problem. It has many applications, and it
  is NP-hard. This problem relates to the scheduling problem and it is denoted by P|rj |Lmax.
  The multiprocessor scheduling problem is defined as follows: tasks have to be executed on
  several parallel identical processors. We must find where and when each task will be executed,
  such that the maximum lateness is minimum. The duration, release time and due date of each
  task are known. Preemption on processors is not allowed. A lot of research in scheduling has
  concentrated on the construction of the nondelay schedule. A nondelay schedule is a feasible
  schedule in which no processor is kept idle at a time when it could begin processing a task. An
  inserted idle time schedule (IIT) as a feasible schedule in which the processor is kept idle at a
  time when it could begin processing a task. The goal of this paper is to propose an IIT schedule
  for the P|rj|Lmax problem. We propose an approximate IIT algorithm named ELS/IIT (earliest
  latest start/ inserted idle time) and depth first branch and bound algorithm, which produces a feasible IIT (inserted idle time) schedule for a fixed maximum lateness L. The algorithm
  may be used in a binary search mode to find the smallest maximum lateness. The branch and
  bound algorithm is based on the earliest latest start/ inserted idle time branching strategy.
  Two new dominance criterions between decision nodes are used. A new method for evaluating
  unfeasible partial solutions was designed. To illustrate the effectiveness of this approach we
  tested algorithms on instances, which were randomly generated with the number of jobs from
  50 to 300. Refs 14. Tables 5.
metadata.lang: en_GB
metadata.name: dc.language.iso
metadata.value: ru
metadata.lang: en_GB
metadata.name: dc.publisher
metadata.value: St Petersburg State University
metadata.lang: en_GB
metadata.name: dc.relation.ispartofseries
metadata.value: Vestnik of Saint Petersburg University. Series 10. Applied Mathematics. Computer Science. Control Processes;
metadata.lang: -
metadata.name: dc.subject
metadata.value: parallel identical processors
metadata.lang: en_GB
metadata.name: dc.subject
metadata.value: branch and bound algorithm
metadata.lang: en_GB
metadata.name: dc.subject
metadata.value: maximum lateness
metadata.lang: en_GB
metadata.name: dc.title
metadata.value: Scheduling problem to minimize the maximum lateness for parallel processors
metadata.lang: en_GB
metadata.name: dc.type
metadata.value: Article
metadata.lang: en_GB
resources.filename: 05-Grigoreva.pdf
resources.url: https://dspace.spbu.ru/bitstream/11701/5996/1/05-Grigoreva.pdf
resources.format: Adobe PDF
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